1. Field of the Invention
The present invention relates to differential switching circuitry for use, for example, in digital-to-analog converters.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows parts of a previously-considered current-switched digital-to-analog converter (DAC) 1. The DAC 1 is designed to convert an n-bit digital input word into a corresponding analog output signal.
The DAC 1 includes a plurality of individual binary-weighted current sources 2.sub.1 to 2.sub.n corresponding respectively to the n bits of the digital input word applied to the DAC. Each current source passes a substantially constant current, the current values passed by the different current sources being binary-weighted such that the current source 2.sub.1 corresponding to a least-significant-bit of the digital input word passes a current I, the current source 2.sub.2 corresponding to the next-least-significant-bit of the digital input word passes a current 2I, and so on for each successive current source of the converter.
The DAC 1 further includes a plurality of differential switching circuits 4.sub.1 to 4.sub.n corresponding respectively to the n current sources 2.sub.1 to 2.sub.n. Each differential switching circuit 4 is connected to its corresponding current source 2 and switches the current produced by the current source either to a first terminal connected to a first connection line A of the converter or a second terminal connected to a second connection line B of the converter. The differential switching circuit receives one bit of the digital input word (for example the differential switching circuit 4.sub.1 receives the least-significant-bit of the input word) and selects either its first terminal or its second terminal in accordance with the value of the bit concerned. A first output current I.sub.A of the DAC is the sum of the respective currents delivered to the differential-switching-circuit first terminals, and a second output current I.sub.B of the DAC is the sum of the respective currents delivered to the differential-switching-circuit second terminals. The analog output signal is the voltage difference V.sub.A -V.sub.B between a voltage V.sub.A produced by sinking the first output current I.sub.A of the DAC 1 into a resistance R and a voltage V.sub.B produced by sinking the second output current I.sub.B of the converter into another resistance R.
FIG. 2 shows a previously-considered form of differential switching circuit suitable for use in a digital-to-analog-converter such as the FIG. 1 converter.
This differential switching circuit 4 comprises first and second PMOS field effect transistors (FETS) S1 and S2. The respective sources of the transistors S1 and S2 are connected to a common node I.sub.IN to which a corresponding current source (2.sub.1 to .sup.2 n in FIG. 1) is connected. The respective drains of the transistors S1 and S2 are connected to respective first and second output nodes I.sub.OUTA and I.sub.OUTE of the circuit which correspond respectively to the first and second terminals of each of the FIG. 1 differential switching circuits.
Each transistor S1 and S2 has a corresponding driver circuit 6.sub.1 or 6.sub.2 connected to its gate. Complementary input signals IN1 and IN2 are applied respectively to the inputs of the driver circuits 6.sub.1 and 6.sub.2. Each driver circuit buffers and inverts its received input signal IN1 or IN2 to produce a switching signal SW1 or SW2 for its associated transistor S1 or S2 such that, in the steady-state condition, one of the transistors S1 and S2 is on and the other is off. For example, as indicated in FIG. 2 itself, when the input signal IN1 has the high level (H) and the input signal IN2 has the low level (L), the switching signal SW1 (gate drive voltage) for the transistor S1 is at the low level L, causing that transistor to be ON, whereas the switching signal SW2 (gate drive voltage) for the transistor S2 is at the high level H, causing that transistor to be OFF. Thus, in this condition, all of the input current flowing into the common node I.sub.IN is passed to the output node I.sub.OUTA and no current passes to the output node I.sub.OUTB.
When it is desired to change the state of the circuit 4 of FIG. 2 so that the transistor S1 is OFF and the transistor S2 is ON, complementary changes are made simultaneously in the input signals IN1 and IN2 such that the input signal IN1 changes from H to L at the same time as the input signal IN2 changes from L to H. As a result of these complementary changes, it is expected that the transistors S1 and S2 will switch symmetrically, that is that the transistor S1 will turn OFF at exactly the same moment that the transistor S2 turns ON. However, in practice there is inevitably some asymmetry in the turn-ON and turn-OFF speeds. This can result in a momentary glitch at the common node I.sub.IN which may in turn cause glitches at one or both output nodes of the circuit, producing a momentary error in the DAC analog output value until all of the switches have switched completely. These glitches in the analog output signal may be code-dependent and result in harmonic distortion or even non-harmonic spurs in the output spectrum.
As the size of the glitch associated with the switching of the differential switching circuit is dependent on the symmetry of the complementary changes in the input signals IN1 and IN2, much attention has been directed to generating and delivering these input signals to the differential switching circuit synchronously with one another. However, it is found in practice that, even if the input signals are perfectly symmetrical, the drive circuits 6.sub.1 and 6.sub.2 which derive the switching signals from the input signals inevitably introduce asymmetry into the switching signals SW1 and SW2 which actually control the transistors S1 and S2. Such asymmetry results in transient output current distortion in any individual differential switch circuit. Furthermore, in a DAC employing multiple differential switch circuits, it also results in a variation between the switching times of the different circuits. These variations lower the spurious-free dynamic range (SFDR) of the DAC (a measure of the difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth). These variations also lead to code-dependency of the analog output signal of the converter.